When developing components for integration into a system, a number of test procedures are typically performed to ensure that the component will operate in the desired manner when integrated into the system. The development of a hardware component (also referred to herein as a device) typically takes place in a number of stages. Firstly, the functional operation/behavior of the component is defined, for example using a Register Transfer Language (RTL). Two popular RTLs used are VHDL and Verilog. In addition, prior to performing such RTL coding, a behavioral model may be built using a UML™ (Universal Modeling Language) to validate at a transactional level that the design intent is correct. Once an RTL representation of the hardware component has been developed, this is then synthesised into a sequence of hardware elements using any of a number of known synthesising tools. The result of the synthesis is a hardware design that can then be used to produce the actual hardware component, for example using appropriate fabrication of the component on silicon. It is costly to perform test procedures on the component once it has been reduced to hardware. Thus, testing of the RTL representation of the component is typically performed to ensure that the actual hardware generated from that RTL representation will operate correctly.
Such testing of the RTL representation typically involves the use of a testbench model providing a test environment for the RTL representation of the component, which is then run on a simulation tool to produce test results which can be analyzed to determine whether the RTL representation of the component is operating as required. The testbench can be formed in a variety of ways. For example, the testbench could be formed to provide a test environment for testing the RTL representation of the component in isolation, which enables direct control of the input stimuli to the RTL representation of the component. However, this requires a particular testbench to be produced for that component representation. Another approach is to combine that RTL representation of the component to be tested with RTL representations of other components that have already been tested, and with which the component to be tested will interact. Hence, in this approach, a portion of the overall system into which the component is intended to be placed is represented in RTL, and a testbench is then constructed based on that RTL representation of the system portion. This avoids the need to produce a particular testbench specifically for the component to be tested, but results in loss of direct control over the input stimuli to the RTL representation of the particular component to be tested.